Method for manufacturing a digital circuit and digital circuit

ABSTRACT

A method for manufacturing a digital circuit is described including forming a plurality of field effect transistor pairs, connecting the field effect transistors of the field effect transistor pairs such that in response to a first transition from a first state of two nodes of the digital circuit and in response to a second transition from a second state of the nodes of the digital circuit the nodes each have an undefined logic state when, for each field effect transistor pair, the threshold voltages of the field effect transistors of the field effect transistor pair are equal and setting the threshold voltages of the field effect transistors of the field effect transistor pairs such that the nodes each have a predetermined defined logic state in response to the first transition and in response to the second transition.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation-in-part of U.S. application Ser. No. 14/801,868, filed 17 Jul. 2015, the content of it being hereby incorporated by reference in its entirety for all purposes.

TECHNICAL FIELD

The present disclosure relates to a method for manufacturing a digital circuit and a digital circuit.

BACKGROUND

Reverse Engineering (RE) of integrated circuits (ICs) can be considered as one of the most serious threats to semi-conductor industry, since it may be misused by an attacker to steal and/or pirate a circuit design. An attacker who successfully reverse engineers an integrated circuit can fabricate and sell a similar, i.e. cloned circuit, and illegally sell and reveal the design.

Therefore concepts and techniques that thwart reverse engineering of integrated circuits are desirable.

SUMMARY

A method for manufacturing a digital circuit is provided including forming a plurality of field effect transistor pairs, connecting the field effect transistors of the field effect transistor pairs such that in response to a first transition from a first state of two nodes of the digital circuit and in response to a second transition from a second state of the nodes of the digital circuit the nodes each have an undefined logic state when, for each field effect transistor pair, the threshold voltages of the field effect transistors of the field effect transistor pair are equal and setting the threshold voltages of the field effect transistors of the field effect transistor pairs such that the nodes each have a predetermined defined logic state in response to the first transition and in response to the second transition.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various aspects are described with reference to the following drawings, in which:

FIG. 1 shows a flow diagram illustrating a method for manufacturing a digital circuit.

FIG. 2 shows a digital circuit.

FIG. 3 shows a circuit implementing a “Magic Hood” cell for path dependent Boolean secrets, in this example an AND-NOR based Magic Hood cell.

FIG. 4 shows a gate schematic for the circuit of FIG. 3.

FIG. 5 shows a field effect transistor (FET).

FIG. 6 shows the gate schematic of a circuit implementing an AND-NOR based Magic Hood cell for path-dependent Boolean Secrets.

FIG. 7 shows a buffer according to an embodiment.

FIG. 8 shows the gate schematic of a circuit implementing an AND-NOR based Magic Hood cell for path-dependent Boolean secrets.

FIG. 9 shows a circuit implementing a Magic Hood cell for path dependent Boolean secrets that is OR-NAND based.

FIG. 10 shows a circuit implementing an AND-NOR based RSX Flip-Flop.

FIG. 11 shows a circuit implementing an AND-OR-NAND based Magic Hood cell.

FIG. 12 shows a circuit implementing an AND-NOR based Magic Hood cell having multiple feedback.

FIG. 13 shows a circuit implmenting a Magic Hood cell based on self-dual ND2-NR2 gates.

FIG. 14 shows a self-dual NAND3-NOR3 gate U_(ND3-NR3) 1400.

FIG. 15 shows a circuit implementing a Magic Hood cell based on self-dual NAND3-NOR3 gates featuring multiple feedback paths.

FIG. 16 shows another example for a gate representing a self-dual Boolean Function.

DESCRIPTION

The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and aspects of this disclosure in which the invention may be practiced. Other aspects may be utilized and structural, logical and electrical changes may be made without departing from the scope of the invention. The various aspects of this disclosure are not necessarily mutually exclusive, as some aspects of this disclosure can be combined with one or more other aspects of this disclosure to form new aspects.

Reverse engineering (RE) can be hindered by deploying camouflage circuits. However, these typically require process technology extensions like doping profile modifications, faked contacts or vias and/or entail significantly increased area and energy consumption. Thus, these measures are often too expensive for mass products.

Indistinguishable yet Complementary Bit Cells, ICBC-X (existing in two flavors or types, namely ICBC-1 and ICBC-0) representing gates that respond to an appropriate challenge by outputting a robust logical one or a robust logical zero, respectively, cannot be easily distinguished by means of Reverse Engineering (RE) and other analysis methods, i.e. attacks to Chip Card Controllers and Security ICs.

The ICBC-X's physical design is (sufficiently) symmetric in terms of its layout, i.e. its active regions, poly-silicon gates, contacts, metal connectivity etc. However, the ICBC-X's nMOS and pMOS components (i.e. nMOS and pMOS field effect transistors) feature appropriately different threshold voltages (Vth) resulting in the robust transfer characteristics of the ICBC-X when challenged with an input pattern that would otherwise cause the circuit to enter a metastable state.

Since process options “regular Vth” and “high Vth” can be used to realize an ICBC-X, no process change is required, provided a mixed-Vth scenario for the Security IC under consideration can be assumed. Further, ICBC-1 and ICBC-0 are static CMOS gates that can be implemented as elements of Standard Cell Libraries.

Application examples include “dynamical” TIE-1 and TIE-0 cells, i.e. TIE cells that can be switched between logically valid and invalid states, representing e.g. bits of a secret key or other pieces of confidential information.

Moreover, ICBC-X instances can be combined with standard logic gates to achieve RE-resistant data paths and ICBC-Xs can be concatenated to realize dynamical TIE tree structures. Session key generation as well as address-dependent memory encryption configuration are also possible.

In addition to that, after roll-out, i.e. after the ICBC-X's initial (e.g. random) configuration, the selected configuration can then be stored in a NVM (non-volatile memory), e.g. of a chip (e.g. a chip card module) including the ICBC-X, for subsequent use in the field. This may even allow for robust and RE-resistant chip-individual pieces of information.

Since a multitude of ICBC-X instances can be distributed irregularly across an IC's entire Semi-Custom portion and because these instances can be accessed in irregular, even random, temporal order, the ICBC-X concept tremendously increases the difficulty, risk and effort for all relevant Security IC attack scenarios like Reverse Engineering, Photon Emission, Laser Voltage Probing, etc.

The basic ICBC-X concept can be seen to rest upon resolving conventionally metastable states or metastable state transitions of (bistable) feedback circuitry by deploying (MOS) transistors (in general switches) with different threshold voltages (in general state transition characteristics) in order to achieve robust ICBC-X state transitions, whereupon the nature of any given ICBC-X instance (X=1 or 0?) remains concealed for an attacker employing relevant Security IC attack scenarios like Reverse Engineering, Photon Emission, Laser Voltage Probing, etc.

ICBC-X circuits as described above exhibit bistable feedback circuitry with

one precharge state (ICBC-X outputs (Z, Y) either at (1, 1) or at (0, 0)) and

one “forbidden transition” of the ICBC-X's outputs:

either (Z, Y)=(1, 1)→(X, not(X)) or (Z, Y)=(0, 0)→(X, not(X),

depending on the respective ICBC-X circuit design.

In contrast with that, according to various embodiments, ICBC-X circuitry is provided that exhibit both bistable and multiple-stable feedback circuitry with

(at least) two different precharge state (outputs (Z, Y) at (1, 1) and at (0, 0), depending on the respective control input signal states) and

(at least) two different “forbidden transitions” of the ICBC-X's outputs:

(Z, Y)=(1, 1)→(X1, not(X1)) or (Z, Y)=(0, 0)→(X0, not(X0),

depending on the respective control input signal transitions,

where the Boolean secrets X1 and X0 may be equal (X1=X0) or complementary (X1=not(X0)), depending on the respective threshold voltage configurations of the ICBC-X's field effect transistors (FETs), e.g. nMOS (n channel metal oxide semiconductor) and pMOS (p channel MOS) FETs.

Since X1 and X0 may be chosen independently, this results in four different ICBC-X incarnations featuring the same physical layout, but differing in their (e.g. CMOS) threshold voltage configurations, and can thus be seen to representing four “Magic Hoods” for Boolean Secrets. Moreover, the independency of X1 and X0 corresponds to a path-dependency of the Boolean Secrets, i.e. the secret (X1 or X0) does not only depend on the input control signal state but also on the way (i.e. on the transition) this state has been arrived at.

According to one embodiment, a method for manufacturing a circuit is described which efficiently allows increasing the necessary effort for a successful reverse engineering of a circuit, e.g. on a chip, by for example providing ICBC-X circuits with multiple precharge states and multiple “forbidden” transitions.

FIG. 1 shows a flow diagram 100.

The flow diagram 100 illustrates a method for manufacturing a digital circuit.

In 101, a plurality of field effect transistor pairs are formed.

In 102, the field effect transistors of the field effect transistor pairs are connected such that in response to a first transition from a first state of two nodes of the digital circuit and in response to a second transition from a second state of the nodes of the digital circuit the nodes each have an undefined logic state when, for each field effect transistor pair, the threshold voltages of the field effect transistors of the field effect transistor pair are equal.

In 103, the threshold voltages of the field effect transistors of the field effect transistor pairs are set such that the nodes each have a predetermined defined logic state in response to the first transition and in response to the second transition.

In other words, according to one embodiment, metastable states of a circuit caused by forbidden transitions are shifted to predefined stable states by setting the threshold voltages of the transistors (and, thus the relation of the threshold voltages of the transistors) of the circuit accordingly. The threshold voltage of a field effect transistor may for example be set by a certain doping of a region (e.g. a channel region) of the field effect transistor. For example, for each field effect transistor pair, the two field effect transistors of the pair may be differently doped.

The field effect transistors of the field effect transistor pair may be geometrically identically designed (i.e. may have same transistor dimensions such as channel width, channel length, source region shape and dimension and drain region shape and dimension). In other words, field effect transistors may be paired based on their identical geometrical design. Thus, optical inspection reveals no difference between the field effect transistors.

The field effect transistors are manufactured to have different threshold voltages such that the nodes each have a predetermined defined logic state in response to the first transition and in response to the second transition. For example, the field effect transistors are manufactured in a way such that the expected value of the difference of their threshold voltages is a multiple of the standard deviation of the difference of their threshold voltages.

It further be noted that in the manufacturing of a digital circuit, the threshold voltages are typically set before the field effect transistors are interconnected. In other words, 103 of the method illustrated in FIG. 1, may be performed before 102, e.g. as a part of 101.

It should further be noted that the threshold voltage of a field effect transistor may be set such that the field effect transistor is always on or always off, e.g. to be higher than or equal to a high supply potential of the digital circuit (VDD) or lower than or equal to a low supply potential of the digital circuit (VSS).

The transitions are for example transitions from different precharge states of the nodes of the circuit. Each transition can be seen as a forbidden transition, meaning a transition which would lead to an undefined logic state when, for each pair, the threshold voltages of the field effect transistors of the pair (in other words the threshold voltages within each pair) were equal. The circuit may be a bistable or multistable circuit wherein the threshold voltages are selected (and set) such that it enters a first state of its (e.g. plurality of) stable states in response to the first transition and a second state of its stable states in response to the second transition, wherein the first state and the second state may be the same states or different states.

One or more digital circuits as manufactured by the method described in FIG. 1 may be included in the chip to prevent reverse engineering of the chip, e.g. a chip card module. According to one embodiment, the one or more digital circuits may then be operated by supplying inputs causing the first transition or the second transition or both, i.e. operated such that the nodes of the digital circuit would each have an undefined logic state when, for each field effect transistor pair, the threshold voltages of the field effect transistors of the field effect transistor pair were equal. Since the threshold voltages are set such that the nodes have, instead, a predetermined defined logic state in response to the input, an output of the digital circuit based on the logic state of the nodes may be further processed by another component. This output may be regarded as a secret since it is based on the logic state of the nodes which depends on the relation of the threshold voltages of the field effect transistors which cannot be easily determined by reverse engineering.

An example of a circuit manufactured according to the method illustrated in FIG. 1 is illustrated in FIG. 2.

FIG. 2 shows a digital circuit 200.

The digital circuit 200 includes (two or more) field effect transistor pairs 201, 202 including field effect transistors connected such that in response to a first transition from a first state of two nodes of the digital circuit and in response to a second transition from a second state of the nodes of the digital circuit the nodes each have an undefined logic state when, for each field effect transistor pair, the threshold voltages of the field effect transistors of the field effect transistor pair are equal, wherein, for each field effect transistor pair, the threshold voltages of the field effect transistors of the field effect transistor pair differ by at least 10 mV such that the nodes each have a predetermined defined logic state in response to the first transition and in response to the second transition.

In the following, various embodiments are given.

Embodiment 1 is a method for manufacturing a digital circuit as illustrated in FIG. 1.

Embodiment 2 includes the method of embodiment 1, including forming outputs for signals representing the logic states of the nodes.

Embodiment 3 includes the method according to embodiment 2, including forming a further circuit component and a connection for supplying the signal to the further circuit component.

Embodiment 4 includes the method according to embodiment 3, wherein the further circuit component is a logic gate.

Embodiment 5 includes the method according to embodiment 3 or 4, wherein the further circuit component is a flip-flop.

Embodiment 6 includes the method according to any one of embodiments 1 to 5, wherein, for each field effect transistor pair, the two field effect transistors of the field effect transistor pair are both n channel field effect transistors or the two field effect transistors of the field effect transistor pair are both p channel field effect transistors.

Embodiment 7 includes the method according to any one of embodiments 1 to 6, wherein the field effect transistors of the field effect transistor pairs are MOSFETs.

Embodiment 8 includes the method according to any one of embodiments 1 to 7, including forming one or more pairs of competing paths such that, for each field effect transistor pair, the two field effect transistors are in different competing paths of a pair of competing paths.

Embodiment 9 includes the method according to embodiment 8, including connecting the one or more pairs of competing paths such that the logic states of the nodes depend on the result of the competition between the competing paths of the one or more pairs of competing paths.

Embodiment 10 includes the method of embodiment 8 or 9, including connecting the one or more pairs of competing paths and the nodes such that for each pair of competing paths, the competing paths are connected to different ones of the two nodes and the electrical state of the node connected to one of the competing paths is fed back to the other of the competing paths to hinder it in a competition of the competing paths.

Embodiment 11 includes the method of any one of embodiments 8 to 10 including forming a first sub-circuit of the digital circuit implementing a first Boolean function and a second sub-circuit of the digital circuit implementing a second Boolean function wherein, for each pair of competing paths, one competing path is in the first sub-circuit and one competing path is in the second sub-circuit.

Embodiment 12 includes the method of embodiment 11, including connecting an output of the first sub-circuit with an input of the second sub-circuit and an output of the second sub-circuit with an input of the first sub-circuit.

Embodiment 13 includes the method of embodiment 11 or 12, wherein the first Boolean function and the second Boolean function are self-dual Boolean functions.

Embodiment 14 includes the method of any one of embodiments 11 to 13, wherein the first Boolean function and the second Boolean function are the same Boolean function.

Embodiment 15 includes the method of any one of embodiments 1 to 14, wherein the plurality of field effect transistor pairs includes one or more pull-up field effect transistor pairs each having a field effect transistor in a first pull-up path and a field effect transistor in a second pull-up path and including connecting the first pull-up path to one of the two nodes and the second pull-up path to the other of the two nodes.

Embodiment 16 includes the method of any one of embodiments 11 to 15, including setting, for each pull-up field effect transistor pair, the threshold voltage of the field effect transistor in the first pull-up path to be lower than the threshold voltage of the field effect transistor in the second pull-up path.

Embodiment 17 includes the method of any one of embodiments 1 to 16, wherein the plurality of field effect transistor pairs includes one or more pull-down field effect transistor pairs each having a field effect transistor in a first pull-down path and a field effect transistor in a second pull-down path and including connecting the first pull-down path to one of the two nodes and the second pull-down path to the other of the two nodes.

Embodiment 18 includes the method of embodiment 17, including setting, for each pull-down field effect transistor pair, the threshold voltage of the field effect transistor in the first pull-down path to be lower than the threshold voltage of the field effect transistor in the second pull-down path.

Embodiment 19 includes the method of any one of embodiments 1 to 18, including connecting the field effect transistors of the field effect transistor pairs to pull-up paths and pull-down paths connected to the two nodes and setting the threshold voltages of the field effect transistors of the pull-up paths independently from the threshold voltages of the field effect transistors of the pull-down paths.

Embodiment 20 includes the method according to any one of embodiments 1 to 19, including forming the plurality of field effect transistors in CMOS technology.

Embodiment 21 includes the method according to any one of embodiments 1 to 20, wherein, for each of the nodes, the predetermined defined logic state is a logic 0 or a logic 1.

Embodiment 22 includes the method according to any one of embodiments 1 to 21, wherein, for each field effect transistor pair, the field effect transistors of the field effect transistor pair are formed to substantially have the same dimensions.

Embodiment 23 includes the method according to any one of embodiments 1 to 22, including forming the digital circuit such that the first transition and the second transition occur in response to a predetermined input, including one or more input signals supplied to field effect transistors of the field effect transistor pairs.

Embodiment 24 includes the method of any one of embodiments 1 to 23, wherein the first transition is a pulling up of the nodes and the method includes connecting the nodes such that, when one of the nodes has been pulled up, it prevents the other node from being pulled up.

Embodiment 25 includes the method of any one of embodiments 1 to 24, wherein the second transition is a pulling down of the nodes and the method includes connecting the nodes such that, when one of the nodes has been pulled down, it prevents the other node from being pulled down.

Embodiment 26 is a digital circuit as illustrated in FIG. 2.

Embodiment 27 includes the digital circuit of embodiment 26, wherein, for each field effect transistor pair, the threshold voltages of the field effect transistors of the field effect transistor pair differ by at least 20 mV, differ by at least 30 mV or differ by at least 50 mV.

It should be noted that embodiments described in context with the method described with reference to FIG. 1 are analogously valid for the digital circuit 200 and vice versa.

In the following, embodiments are described in more detail.

FIG. 3 shows a circuit 300 implementing a “Magic Hood” cell for path dependent Boolean secrets, in this example an AND-NOR based Magic Hood cell.

FIG. 4 shows a gate schematic for the circuit 300.

The circuit 300 has two control inputs RN and S and two outputs Z and Y. The circuit includes a first AND-NOR 301, 401, a second AND-NOR 302, 402, a first inverter 303, 403 and a second inverter 304, 404.

The first AND-NOR 301 includes a first p channel FET 305 whose source is connected to the high supply potential (VDD) and whose gate is supplied with the signal S. The first AND-NOR 301 further includes a second p channel FET 306 whose source is connected to the high supply potential (VDD). The drains of the first p channel FET 305 and the second p channel FET 306 are connected to the source of a third p channel FET 307 whose gate is supplied with the signal RN and whose drain is connected to a first output node (or feedback node) 308 whose state is referred to by SY.

The first AND-NOR 301 further includes a first n channel FET 309 whose source is connected to the low supply potential (VSS), whose gate is supplied with the signal RN and whose drain is connected to the first output node 308. The first AND-NOR 301 further includes a second n channel FET 310 whose source is connected to the low supply potential (VSS) and whose drain is connected to the source of a third n channel FET 311 whose gate is supplied with the signal S and whose drain is connected to the first output node 308.

The second AND-NOR 302 includes a fourth p channel FET 312 whose source is connected to the high supply potential (VDD) and whose gate is supplied with the signal S. The second AND-NOR 302 further includes a fifth p channel FET 313 whose source is connected to the high supply potential (VDD). The drains of the fourth p channel FET 312 and the fifth p channel FET 313 are connected to the source of a sixth p channel FET 314 whose gate is supplied with the signal RN and whose drain is connected to a second output node (or feedback node) 315 whose state is referred to by SZ.

The second AND-NOR 302 further includes a fourth n channel FET 316 whose source is connected to the low supply potential (VSS), whose gate is supplied with the signal RN and whose drain is connected to the second output node 315. The second AND-NOR 302 further includes a fifth n channel FET 317 whose source is connected to the low supply potential (VSS) and whose drain is connected to the source of a sixth n channel FET 318 whose gate is supplied with the signal S and whose drain is connected to the second output node 315.

The first output node 308 is further connected to the input of the first inverter 303 whose output is the output Y. Further, the first output node 308 is connected to the gates of the fifth p channel FET 313 and the fifth n channel FET 317.

The second output node 315 is further connected to the input of the second inverter 304 whose output is the output Z. Further, the second output node 315 is connected to the gates of the second p channel FET 306 and the second n channel FET 310.

The inverters 303, 304 are for example realized by a p channel FET and an n channel FET connected serially between the high supply potential and the low potential which receive the inverter's 303, 304 input at their gates and wherein the node between them is the output node of the respective inverter 303, 304.

In the following, it is assumed that p channel FETs are implemented by pMOS transistors (also referred to as pMOS devices) and n channel FETs are implemented by nMOS transistors (also referred to as nMOS devices). The circuit 300 as well as the circuits described in the following are for example implemented in CMOS (Complementary Metal Oxide Semiconductor) technology.

For RN=1 the circuit 300 is in its first precharge state:

RN=1=>(SZ, SY)=(0, 0)=>(Z, Y)=(1, 1).

For (RN, S)=(0, 0) the circuit 300 is in its second precharge state:

(RN, S)=(0, 0)=>(SZ, SY)=(1, 1)=>(Z, Y)=(0, 0).

The first forbidden transition is given by

(RN, S)=(1, 1)→(0, 1),

whereby the two competing pull-up paths including the serial connections of the fifth p channel FET 313, denoted by TPZ0 (having threshold voltage Vth(PZ0)), and the sixth p channel FET 314, denoted by TPZ1 (having threshold voltage Vth(PZ1)), for SZ, as well as the second p channel FET 306, denoted by TPY0 (having threshold voltage Vth(PY0)), and the third p channel FET 307, denoted by TPY1 (having threshold voltage Vth(PY1)), for SY, are activated.

Thus, the two different threshold voltage configurations

Vth(PZ1)<Vth(PY1); Vth(PZ0)<Vth(PY0) and

Vth(PZ1)>Vth(PY1); Vth(PZ0)>Vth(PY0)

correspond to the two different values X1=0 and X1=1 for the first forbidden transition

(RN, S)=(1, 1)→(0, 1)=>(Z, Y)=(1, 1)→(X1, not(X1)).

The second forbidden transition is given by

(RN, S)=(0, 0)→(0, 1),

whereby the two competing pull-down paths, including the serial connections of the fifth n channel FET 317, denoted by TNZ0, and the sixth n channel FET 318, denoted by TNZ1, for SZ, as well as the second n channel FET 310, denoted by TNY0, and the third n channel FET 311, denoted by TNY1 for SY, are activated.

Thus, the two different threshold voltage configurations

Vth(NZ1)<Vth(NY1); Vth(NZ0)<Vth(NY0) and

Vth(NZ1)>Vth(NY1); Vth(NZ0)>Vth(NY0)

correspond to the two different values X0=1 and X0=0 for the second forbidden transition

(RN, S)=(0, 0)→(0, 1)=>(Z, Y)=(0, 0)→(X0, not(X0)).

Possibilities to set the threshold voltage of a field effect transistor are described in the following with reference to FIG. 5.

FIG. 5 shows a field effect transistor (FET) 500.

The FET 500 includes a source region 501, a drain region 502, a gate 503 and a channel region 504. The channel region 504 may lie in a substrate or in a well within the substrate.

The source region 501 has an extension 505 and a halo 506. Similarly, the drain region 502 has an extension 507 and a halo 508.

The threshold voltage of the FET 500 can be set by setting appropriate doping concentrations in the channel region 504, of the halos 506, 508 and/or setting the doping concentration in the extensions 505, 507.

FIG. 6 shows the gate schematic of a circuit 600 implementing an AND-NOR based Magic Hood cell for path-dependent Boolean Secrets.

Similarly to the circuit 300 as illustrated in FIG. 4, the circuit 600 includes a first AND-NOR 601, a second AND-NOR 602, a first inverter 603 and a second inverter 604. However, in comparison with the circuit 300, a first buffer 605 and a second buffer 606 are connected between the outputs of the AND-NOR gates 601, 602 and the first output nodes 308 (SY) and the second output node 315 (SZ), respectively, in order to increase the robustness of the Magic Hood cell with respect to random process variation of the relevant threshold voltages.

The buffers 605, 606 for example exhibit the same physical design but may differ with respect to their respective threshold voltage configurations of their respective (e.g. CMOS) components, resulting in different delays(and slopes) t_(r)(Y) and t_(r)(Z) of rising edges, and delays t_(f)(Y) and t_(f)(Z) of falling edges of SY and SZ, respectively. Thus, the time-asymmetry of the transitions of SY and SZ, due to the above described asymmetric Vth configurations of the AND-NOR gates ANR-Y and ANR-Z may be increased.

As for the first forbidden transition, i.e.

(RN, S)=(1, 1)→(0, 1),

the two competing pull-up paths for the outputs of the AND-NORs 601, 602, consisting in the serial connections of pMOS devices TPZ1 and TPZ0, as well as TPY1 and TPY0, are activated.

Thus, the two different threshold voltage configurations

Vth(PZ1)<Vth(PY1); Vth(PZ0)<Vth(PY0) and

Vth(PZ1)>Vth(PY1); Vth(PZ0)>Vth(PY0),

(corresponding to the two different values X1=0 and X1=1 for the first forbidden transition) may be complemented by threshold voltage configurations in the buffers 605, 606 resulting in

t_(r)(Z)<t_(r)(Y) and

t_(r)(Z)>t_(r)(Y), respectively.

As a result, the forbidden transition

(RN, S)=(1, 1)→(0, 1)=>(Z, Y)=(1, 1)→(X1, not(X1))

is more robust against process variations than the circuit of FIGS. 3 and 4.

An example for an implementation of the buffers 605, 606 in order to illustrate the realization of the above inequalities t_(r)(Z)<t_(r)(Y) and t_(r)(Z)>t_(r)(Y) is given in FIG. 7.

FIG. 7 shows a buffer 700 according to an embodiment.

The buffer 700 includes a first inverter 701 and a second inverter 702, which are serially connected such that the first inverter 701 receives an input A and the second inverter 702 receives the output of the first inverter 701 and outputs an output Z of the buffer 700.

Each inverter 701, 702 is realized by a pMOS 703, 704 and an nMOS 705, 706 connected serially between the high supply potential and the low potential which receive the inverter's 701, 702 input at their gates and wherein the node between them is the output node of the inverter 701, 702.

Thus, t_(r)(Z)<t_(r)(Y) may be realized by choosing in the second buffer 606 the threshold voltages of the nMOS device 705 in the first inverter 701 and of the pMOS device 704 in the second inverter 702 to be lower than the threshold voltages of the nMOS device 705 in the first inverter 701 and of the pMOS device 704 in the second inverter 702 of the first buffer 605.

On the other hand, t_(r)(Z)>t_(r)(Y) may be realized by choosing in the second buffer 606 the threshold voltages of the nMOS device 705 in the first inverter 701 and of the pMOS device 704 in the second inverter 702 to be higher than the threshold voltages of the nMOS device 705 in the first inverter 701 and of the pMOS device 704 in the second inverter 702 of the first buffer 605.

As for the second forbidden transition, i.e.

(RN, S)=(0, 0)→(0, 1),

the two competing pull-down paths for the outputs of the first AND-NOR 601 and the second AND-NOR 602 including the serial connections of nMOS devices TNZ1 and TNZ0 as well as TNY1 and TNY0, are activated.

Thus, the two different threshold voltage configurations

Vth(NZ1)<Vth(NY1); Vth(NZ0)<Vth(NY0) and

Vth(NZ1)>Vth(NY1); Vth(NZ0)>Vth(NY0)

(corresponding to the two different values X0=1 and X0=0 for the second forbidden transition) may be complemented by threshold voltage configurations in buffers 605, 606 resulting in

t_(f)(Z)<t_(f)(Y) and

t_(f)(Z)>t_(f)(Y), respectively.

As a result, the forbidden transition

(RN, S)=(0, 0)→(0, 1)=>(Z, Y)=(0, 0)→(X0, not(X0))

is more robust against process variations than the Magic Hood cell of FIGS. 3 and 4.

With the buffer implementation illustrated in FIG. 7, t_(f)(Z)<t_(f)(Y) may be realized by choosing in the second buffer 606 the threshold voltages of the pMOS device 703 in the first inverter 701 and of the nMOS device 706 in the second inverter 702 to be lower than the threshold voltages of the pMOS device 703 in the first inverter 701 and of the nMOS device 706 in the second inverter 702 of the first buffer 605.

On the other hand, t_(f)(Z)>t_(f)(Y) may be realized by choosing in the second buffer 606 the threshold voltages of the pMOS device 703 in the first inverter 701 and of the nMOS device 706 in the second inverter 702 to be higher than the threshold voltages of the pMOS device 703 in the first inverter 701 and of the nMOS device 706 in the second inverter 702 of the first buffer 605.

For the buffers 605, 606 also other options than two inverters may be used. For example, the buffers 605, 606 can also be chosen to include an inverter combined with an inverting Schmitt-Trigger circuit, whereby, with adequate Vth configurations, it is possible to increase even further the robustness margin against threshold variations caused by random process variations.

FIG. 8 shows the gate schematic of a circuit 800 implementing an AND-NOR based Magic Hood cell for path-dependent Boolean secrets.

Similarly to the circuit 300 as illustrated in FIG. 4, the circuit 800 includes a first AND-NOR 801, a second AND-NOR 802, a first inverter 803 and a second inverter 804.

However, in comparison with the Magic Hood cell of FIG. 4, four additional buffers 805, 806, 807, 808 are connected between the control inputs RN and S and the corresponding inputs of the two AND-NOR gates 801, 802 respectively, in order to increase the robustness of the Magic Hood cell with respect to random process variation of the relevant threshold voltages.

As for the first forbidden transition, i.e.

(RN, S)=(1, 1)→(0, 1),

the two competing pull-up paths for the outputs of the AND-NOR gates 801, 802 including the serial connections of pMOS devices TPZ1 and TPZ0, as well as TPY1 and TPY0, are activated.

Thus, the two different threshold voltage configurations

Vth(PZ1)<Vth(PY1); Vth(PZ0)<Vth(PY0) and

Vth(PZ1)>Vth(PY1); Vth(PZ0)>Vth(PY0),

(corresponding to the two different values X1=0 and X1=1 for the first forbidden transition) may be complemented by threshold voltage configurations in the first buffer 805 (having falling delay t_(f)(YR)) and the third buffer 807 (having falling delay t_(f)(ZR)) resulting in

t_(f)(ZR)<t_(f)(YR) and

t_(f)(ZR)>t_(f)(YR), respectively.

As a result, the “forbidden transition”

(RN, S)=(1, 1)→(0, 1)=>(Z, Y)=(1, 1)→(X1, not(X1))

is more robust against process variations than Magic Hood cell of FIGS. 3 and 4.

With the buffer implementation illustrated in FIG. 7, t_(f)(ZR)<t_(f)(YR) may be realized by choosing in the third buffer 807 the threshold voltages of the pMOS device 703 in the first inverter 701 and of the nMOS device 706 in the second inverter 702 to be lower than the threshold voltages of the pMOS device 703 in the first inverter 701 and of the nMOS device 706 in the second inverter 702 of the first buffer 805.

On the other hand, t_(f)(ZR)>t_(f)(YR) may be realized by choosing in the third buffer 807 the threshold voltages of the pMOS device 703 in the first inverter 701 and of the nMOS device 706 in the second inverter 702 to be higher than the threshold voltages of the pMOS device 703 in the first inverter 701 and of the nMOS device 706 in the second inverter 702 of the first buffer 805.

As for the second forbidden transition, i.e.

(RN, S)=(0, 0)→(0, 1),

the two competing pull-down paths for the outputs of the AND-NOR gates 801, 802 including the serial connections of nMOS devices TNZ1 and TNZ0 as well as TNY1 and TNY0, are activated.

Thus, the two different threshold voltage configurations

Vth(NZ1)<Vth(NY1); Vth(NZ0)<Vth(NY0) and

Vth(NZ1)>Vth(NY1); Vth(NZ0)>Vth(NY0)

(corresponding to the two different values X0=1 and X0=0 for the second forbidden transition) may be complemented by threshold voltage configurations in the fourth buffer 808 (having rising delay t_(r)(ZS)) and the second buffer 806 (having rising delay t_(r)(YS)) resulting in

t_(r)(ZS)<t_(r)(YS) and

t_(r)(ZS)>t_(r)(YS), respectively.

As a result, the “forbidden transition”

(RN, S)=(0, 0)→(0, 1)=>(Z, Y)=(0, 0)→(X0, not(X0))

is more robust against process variations than the Magic Hood cell of FIGS. 3 and 4.

With the buffer implementation illustrated in FIG. 7, t_(r)(ZS)<t_(r)(YS) may be realized by choosing in the fourth buffer 808 the threshold voltages of the nMOS device 705 in the first inverter 701 and of the pMOS device 704 in the second inverter 702 to be lower than the threshold voltages of the nMOS device 705 in the first inverter 701 and of the pMOS device 704 in the second inverter 702 of the second buffer 806.

On the other hand, t_(r)(ZS)>t_(r)(YS) may be realized by choosing in the fourth buffer 808 the threshold voltages of the nMOS device 705 in the first inverter 701 and of the pMOS device 704 in the second inverter 702 to be higher than the threshold voltages of the nMOS device 705 in the first inverter 701 and of the pMOS device 704 in the second inverter 702 of the second buffer 806.

It should be noted that in order to save transistor count, instead of the buffers 805, 806, 807, 808 also inverters may be used between the input control signals and the corresponding inputs of the AND-NOR gates 801, 802. For this, the low-active RN can be replaced by a high-active R and the high-active S can be replaced by a low-active SN.

FIG. 9 shows a circuit 900 implementing a Magic Hood cell for path dependent Boolean secrets that is OR-NAND based.

The circuit 900 has two control inputs SN and R and two outputs Z and Y. The circuit includes a first OR-NAND 901, a second OR-NAND 902, a first inverter 903 and a second inverter 904.

The first OR-NAND 901 includes a first p channel FET 905 whose source is connected to the high supply potential (VDD) and whose gate is supplied with the signal R and whose drain is connected to a first output node (or feedback node) 908 whose state is referred to by SY. The first OR-NAND 901 further includes a second p channel FET 906 whose source is connected to the high supply potential (VDD) and whose drain is connected to the source of a third p channel FET 907 whose gate is supplied with the signal SN and whose drain is connected to the first output node 908.

The first OR-NAND 901 further includes a first n channel FET 909 whose source is connected to the low supply potential (VSS) and whose gate is supplied with the signal SN. The first OR-NAND 901 further includes a second n channel FET 910 whose source is connected to the low supply potential (VSS). The drains of the first n channel FET 909 and the second n channel FET 910 are connected to the source of a third n channel FET 911 whose gate is supplied with the signal R and whose drain is connected to the first output node 908.

The second OR-NAND 902 includes a fourth p channel FET 912 whose source is connected to the high supply potential (VDD) and whose gate is supplied with the signal R and whose drain is connected to a second output node (or feedback node) 915 whose state is referred to by SZ. The second OR-NAND 902 further includes a fifth p channel FET 913 whose source is connected to the high supply potential (VDD) and whose drain is connected to the source of a sixth p channel FET 914 whose gate is supplied with the signal SN and whose drain is connected to the second output node 915.

The second OR-NAND 902 further includes a fourth n channel FET 916 whose source is connected to the low supply potential (VSS) and whose gate is supplied with the signal SN. The first second OR-NAND 902 further includes a fifth n channel FET 917 whose source is connected to the low supply potential (VSS). The drains of the fourth n channel FET 916 and the fifth n channel FET 910 are connected to the source of a sixth n channel FET 918 whose gate is supplied with the signal R and whose drain is connected to the second output node 915.

The first output node 908 is further connected to the input of the first inverter 903 whose output is the output Y. Further, the first output node 908 is connected to the gates of the fifth p channel FET 913 and the fifth n channel FET 917.

The second output node 915 is further connected to the input of the second inverter 904 whose output is the output Z. Further, the second output node 915 is connected to the gates of the second p channel FET 906 and the second n channel FET 910.

The inverters 903, 904 are for example realized by a p channel FET and an n channel FET connected serially between the high supply potential and the low potential which receive the inverter's 903, 904 input at their gates and wherein the node between them is the output node of the inverter 903, 904.

For R=0 the circuit is in its first precharge state:

R=0=>(SZ, SY)=(1, 1)=>(Z, Y)=(0, 0).

For (R, SN)=(1, 1) the circuit is in its second precharge state:

(R, SN)=(1, 1)=>(SZ, SY)=(0, 0)=>(Z, Y)=(1, 1).

The first forbidden transition is given by

(R, SN)=(0, 0)→(1, 0),

whereby the two competing pull-down paths, including the serial connections of the fifth n channel FET 917, denoted by TNZ0, and the sixth n channel FET 918, denoted by TNZ1, for SZ, as well as the second n channel FET 910, denoted by TNY0, and the third n channel FET 911, denoted by TNY1 for SY, are activated.

Thus, the two different threshold voltage configurations

Vth(NZ1)<Vth(NY1); Vth(NZ0)<Vth(NY0) and

Vth(NZ1)>Vth(NY1); Vth(NZ0)>Vth(NY0)

correspond to the two different values X0=1 and X0=0 for the first forbidden transition

(R, SN)=(0, 0)→(1, 0)=>(Z, Y)=(0, 0)→(X0, not(X0)).

The second forbidden transition is given by

(R, SN)=(1, 1)→(1, 0),

whereby the two competing pull-up paths including the serial connections of the fifth p channel FET 913, denoted by TPZ0 (having threshold voltage Vth(PZ0)), and the sixth p channel FET 914, denoted by TPZ1 (having threshold voltage Vth(PZ1)), for SZ, as well as the second p channel FET 906, denoted by TPY0 (having threshold voltage Vth(PY0)), and the third p channel FET 907, denoted by TPY1 (having threshold voltage Vth(PY1)), for SY, are activated.

Thus, the two different threshold voltage configurations

Vth(PZ1)<Vth(PY1); Vth(PZ0)<Vth(PY0) and

Vth(PZ1)>Vth(PY1); Vth(PZ0)>Vth(PY0)

correspond to the two different values X1=0 and X1=1 for the second forbidden transition

(R, SN)=(1, 1)→(1, 0)=>(Z, Y)=(1, 1)→(X1, not(X1)).

FIG. 10 shows a circuit 1000 implementing an AND-NOR based RSX Flip-Flop, i.e. an Magic Hood cell as described with reference to figures with FIGS. 3 to 6 featuring the additional function of a regular RS-FF.

Similarly to the circuit 600, the circuit 1000 includes a first AND-NOR 1001, a second AND-NOR 1002, a first inverter 1003, a second inverter 1004, a first buffer 1005 and a second buffer 1006.

In addition, the S input of the first AND-NOR 1001 is preceded by a first NOR 1007 which has an input signal SNY and an enable signal EN as inputs. Similarly, the S input of the second AND-NOR 1002 is preceded by a second NOR 1008 which has an input signal SNZ and the enable signal EN as inputs.

The input control signal transition

(RN, SNZ, SNY, EN)=(0, 0, 1, 1)→(0, 0, 1, 0)

causes the output signal transition

(Z, Y)=(0, 0)→(1, 0),

i.e. the SET function of a regular RS-FF.

The input control signal transition

(RN, SNZ, SNY, EN)=(0, 1, 0, 1)→(0, 1, 0, 0)

causes the output signal transition

(Z, Y)=(0, 0)→(0, 1),

i.e. the RESET function of a regular RS-FF.

Besides, the first forbidden MH transition

(RN, SNZ, SNY, EN)=(1, 0, 0, 0)→(0, 0, 0, 0)

results in

(Z, Y)=(1, 1)→(X1, not(X1)),

whereas the second forbidden MH transition

(RN, SNZ, SNY, EN)=(0, 0, 0, 1)→(0, 0, 0, 0)

results in

(Z, Y)=(0, 0)→(X0, not(X0)),

as described above with reference to FIGS. 3 to 6.

FIG. 11 shows a circuit 1100 implementing an AND-OR-NAND based Magic Hood cell. This can be seen as a generalization of the MH cell described with reference to FIGS. 3 to 6.

The circuit 1100 has outputs Y and Z generated by a first inverter 1101 and a second inverter 1102 from the states SY and SZ of two output (or feedback) nodes and has the input signals RN, S1 and S0.

The circuit 1100 includes a first AND-OR-NAND 1103 which receives the state SZ and the signal S0 at its AND inputs, the signal RN at its OR input and the signal S1 at its NAND input and outputs SY.

Similarly, the circuit 1100 includes a second AND-OR-NAND 1104 which receives the state SY and the signal S0 at its AND inputs, the signal RN at its OR input and the signal S1 at its NAND input and outputs SZ.

Thus, there are three control inputs RN, S1 and S0 and three precharge states

-   -   S1=0=>(Z, Y)=(0, 0),     -   (S1, RN)=(1, 1)=>(Z, Y)=(1, 1) and     -   (S1, RN, S0)=(1, 0, 0)=>(Z, Y)=(0, 0),         as well as three forbidden transitions:     -   (S1, RN, S0)=(0, 0, 1)→(1, 0, 1), resulting in (Z, Y)=(0,         0)→(X0, not(X0)),     -   (S1, RN, S0)=(1, 1, 1)→(1, 0, 1), resulting in (Z, Y)=(1,         1)→(X1, not(X1)) and     -   (S1, RN, S0)=(1, 0, 0)→(1, 0, 1), resulting in (Z, Y)=(0,         0)→(X0, not(X0)).

It should be noted that there are only two independent secrets X0 and X1, since there are also only two competing pull-up and pull-down paths within the two AND-OR-NAND gates 1103, 1104.

FIG. 12 shows a circuit 1200 implementing an AND-NOR based Magic Hood cell having multiple feedback, which can be seen as another example for generalizations of the Magic Hood cell of FIGS. 3 to 6.

The circuit 1200 has outputs Y, Z and W generated by a first inverter 1201, a second inverter 1202 and a third inverter 1203 from the states SY, SZ and SW of three output (or feedback) nodes and has the input signals RN and S.

The circuit 1200 includes a first AND-NOR 1204 which receives the states SZ, SW and the signal S at its AND inputs and the signal RN at its NOR input and outputs SY.

Similarly, the circuit 1200 includes a second AND-NOR 1205 which receives the states SY, SW and the signal S at its AND inputs and the signal RN at its NOR input and outputs SZ.

Similarly, the circuit 1200 includes a third AND-NOR 1206 which receives the states SY, SZ and the signal S at its AND inputs and the signal RN at its NOR input and outputs SW.

Depending on the control inputs RN and S there are the two precharge states

RN=1=>(Z, Y, W)=(1, 1, 1) and

(RN, S)=(0, 0)=>(Z, Y, W)=(0, 0, 0)

of the three outputs Z, Y and W.

For (RN, S)=(0, 1) there are three stable states of the outputs:

-   -   (RN, S)=(0, 1)=>either (Z, Y, W)=(1, 0, 0), or (Z, Y, W)=(0,         1, 0) or (Z, Y, W)=(0, 0, 1).

All three output states can be arrived at from one of the two precharge states, either in case of the transition (RN, S)=(1, 1)→(0, 1), by activating simultaneously all the AND-NOR gates' pull-up paths, or in case of the transition

(RN, S)=(0, 0)→(0, 1)

by activating simultaneously all the AND-NOR gates' pull-down paths. Thus, by suitably and independently choosing the Vth configurations for the pull-up and pull-down paths, respectively, nine different incarnations of this MH circuit can be realized, all of them with identical physical design, but pairwise differing from each other in their forbidden transition behavior.

In the following, embodiments are described which allow achieving a higher Magic Hood efficiency defined as the quotient of the number of realisable secrets (i.e. the number of possible different Magic Hood incarnations for a circuit), and the number of necessary FETs (e.g. MOSFETs) of the circuit, compared to embodiments described above such as the circuit 300.

Embodiments described above such as the circuit 300 as well as ICBC-X circuits exhibiting bistable feedback circuitry are based on either NAND or NOR gates, and on either AND-NOR or OR-NAND gates, respectively, i.e. on one specific type of basic Boolean Functions.

In contrast to that, in the following, a unification of the basic Boolean Functions is described on which the Magic Hood cells of the following embodiments are based, i.e. the Magic Hood cells described in the following are based on a class of complex gates representing so-called Self-Dual Boolean Functions (SDBF), that are defined as being their own Dual Function (DF), where the Dual Function F^(D)(A, B, . . . ) of a given Boolean Function F(A, B, . . . ) is defined as

F^(D)(A, B, . . . )=NOT {F(NOT(A), NOT(B), . . . }.

For instance, the DF of the Boolean Function NOR (A, B) is derived to be

-   -   NOR^(D)(A, B)=NOT{NOR (NOT(A), NOT(B)}=NOT{AND (A, B)=NAND (A,         B).

Now, the SDBF on which the following embodiments are based are determined to be of the form

U(T; A, B, . . . )=OR [AND {NOT(T), F (A, B, . . . )}, AND {T, F^(D) (A, B, . . . )}],

for which

U^(D)(T; A, B, . . . )=U (T; A, B, . . . )

holds.

In order to illustrate the benefit of SDBF for MH circuitry, as a first example, the complex gate representing the SDBF

-   -   U_(ND2-NR2)(T; A, B)=OR [AND {NOT(T), NAND (A, B)}, AND {T,         NAND^(D) (A, B)}]=OR [AND {NOT(T), NAND (A, B)}, AND {T, NOR (A,         B)}],         is considered, i.e. a gate representing both the NAND2 (i.e.         NAND with two inputs) and the NOR2 (i.e. NOR with two inputs)         function, depending on an additional transformation parameter T:         for T=0 the SDBF is equivalent to NAND2(A, B) and for T=1 to         NOR2(A, B).

FIG. 13 shows a circuit 1300 corresponding to U_(ND2-NR2), i.e. a transistor implementing a Magic Hood cell based on self-dual NAND2-NOR2 gates.

The circuit 1300 has two control inputs T and S and two outputs Z and Y. The circuit 1300 includes a first unified NAND-NOR 1301, a second unified NAND-NOR 1302, a first inverter 1303 and a second inverter 1304.

The first unified NAND-NOR 1301 includes a first p channel FET 1305 whose source is connected to the high supply potential (VDD) and whose gate is supplied with the signal S. The first unified NAND-NOR 1301 further includes a second p channel FET 1306 whose source is connected to the high supply potential (VDD). The drains of the first p channel FET 1305 and the second p channel FET 1306 are connected to the source of a third p channel FET 1307 whose gate is supplied with the signal T and whose drain is connected to a first output node (or feedback node) 1308 whose state is referred to by SY.

The first unified NAND-NOR 1301 further includes a fourth p channel FET 1309 whose source is connected to the high supply potential, whose gate is connected to the gate of the second p channel FET 1306 and whose drain is connected to the source of a fifth p channel FET 1310 whose gate is supplied with the signal S and whose drain is connected to the first output node 1308.

Further, the first unified NAND-NOR 1301 includes a first n channel FET 1311 whose source is connected to the low supply potential (VSS) and whose gate is supplied with the signal S. The first unified NAND-NOR 1301 further includes a second n channel FET 1312 whose source is connected to the low supply potential (VSS). The drains of the first n channel FET 1311 and the second n channel FET 1312 are connected to the source of a third n channel FET 1313 whose gate is supplied with the signal T and whose drain is connected to the first output node 1308.

The first unified NAND-NOR 1301 further includes a fourth n channel FET 1314 whose source is connected to the low supply potential, whose gate is connected to the gate of the second n channel FET 1312 and whose drain is connected to the source of a fifth n channel FET 1315 whose gate is supplied with the signal S and whose drain is connected to the first output node 1308.

The second unified NAND-NOR 1302 includes a sixth p channel FET 1316 whose source is connected to the high supply potential (VDD) and whose gate is supplied with the signal S. The second unified NAND-NOR 1302 further includes a seventh p channel FET 1317 whose source is connected to the high supply potential (VDD). The drains of the sixth p channel FET 1316 and the seventh p channel FET 1317 are connected to the source of an eighth p channel FET 1318 whose gate is supplied with the signal T and whose drain is connected to a second output node (or feedback node) 1319 whose state is referred to by SZ.

The second unified NAND-NOR 1302 further includes a ninth p channel FET 1320 whose source is connected to the high supply potential, whose gate is connected to the gate of the seventh p channel FET 1317 and whose drain is connected to the source of a tenth p channel FET 1321 whose gate is supplied with the signal S and whose drain is connected to the second output node 1319.

Further, the second unified NAND-NOR 1302 includes a sixth n channel FET 1322 whose source is connected to the low supply potential (VSS) and whose gate is supplied with the signal S. The second unified NAND-NOR 1302 further includes a seventh n channel FET 1323 whose source is connected to the low supply potential (VSS). The drains of the sixth n channel FET 1322 and the seventh n channel FET 1323 are connected to the source of a eighth n channel FET 1324 whose gate is supplied with the signal T and whose drain is connected to the second output node 1319.

The second unified NAND-NOR 1302 further includes a ninth n channel FET 1325 whose source is connected to the low supply potential, whose gate is connected to the gate of the seventh n channel FET 1323 and whose drain is connected to the source of a tenth n channel FET 1326 whose gate is supplied with the signal S and whose drain is connected to the second output node 1319.

The first output node 1308 is further connected to the input of the first inverter 1303 whose output is the output Y. Further, the first output node 1308 is connected to the gates of the ninth p channel FET 1320 and the ninth n channel FET 1325.

The second output node 1319 is further connected to the input of the second inverter 1304 whose output is the output Z. Further, the second output node 1319 is connected to the gates of the fourth p channel FET 1309 and the fourth n channel FET 1314.

The inverters 1303, 1304 are for example realized by a p channel FET and an n channel FET connected serially between the high supply potential and the low potential which receive the inverter's 1303, 1304 input at their gates and wherein the node between them is the output node of the respective inverter 303, 304.

For (T, S)=(0, 0) the circuit 1300 is in a first precharge state:

(T, S)=(0, 0)=>(SZ, SY)=(1, 1)=>(Z, Y)=(0, 0),

and for (T, S)=(1, 1) the circuit is in a second precharge state:

(T, S)=(1, 1)=>(SZ, SY)=(0, 0)=>(Z, Y)=(1, 1).

The first forbidden transition is given by (T, S)=(0, 0)→(0, 1), whereby the two competing pull-down paths, including the serial connections of the tenth n channel FET 1326, denoted by TNZ4, and the ninth n channel FET 1325, denoted by TNZ3, for SZ, as well as the fifth n channel FET 1315, denoted by TNY4, and the fourth n channel FET 1314, denoted by TNY3 for SY, are activated.

Thus, the two different threshold voltage configurations

(N43-1) Vth(NZ4)<Vth(NY4); Vth(NZ3)<Vth(NY3), and

(N43-0) Vth(NZ4)>Vth(NY4); Vth(NZ3)>Vth(NY3)

correspond to the two different values X00=1 and X00=0 for the first forbidden transition:

(T, S)=(0, 0)→(0, 1)=>(Z, Y)=(0, 0)→(X00, not(X00)).

The second forbidden transition is given by (T, S)=(0, 0)→(1, 0), whereby the two competing pull-down paths, including the serial connections of the eighth n channel FET 1324, denoted by TNZ2, and the seventh n channel FET 1323, denoted by TNZ1, for SZ, as well as the third n channel FET 1313, denoted by TNY2, and the second n channel FET 1312, denoted by TNY1 for SY, are activated.

Thus, the two different threshold voltage configurations

(N21-1) Vth(NZ2)<Vth(NY2); Vth(NZ1)<Vth(NY1), and

(N21-0) Vth(NZ2)>Vth(NY2); Vth(NZ1)>Vth(NY1)

correspond to the two different values X01=1 and X01=0 for the second forbidden transition

(T, S)=(0, 0)→(1, 0)=>(Z, Y)=(0, 0)→(X01, not(X01)).

The third forbidden transition is given by (T, S)=(1, 1)→(1, 0), whereby the two competing pull-up paths, including the serial connections of the tenth p channel FET 1321, denoted by TPZ4, and the ninth p channel FET 1320, denoted by TPZ3, for SZ, as well as the fifth p channel FET 1310, denoted by TPY4, and the fourth p channel FET 1309, denoted by TPY3 for SY, are activated.

Thus, the two different threshold voltage configurations

(P43-1) Vth(PZ4)<Vth(PY4); Vth(PZ3)<Vth(PY3), and

(P43-0) Vth(PZ4)>Vth(PY4); Vth(PZ3)>Vth(PY3)

correspond to the two different values X10=0 and X10=1 for the third forbidden transition:

(T, S)=(1, 1)→(1, 0)=>(Z, Y)=(1, 1)→(X10, not(X10)).

The fourth forbidden transition is given by (T, S)=(1, 1)→(0, 1), whereby the two competing pull-up paths, including the serial connections of the eighth p channel FET 1318, denoted by TPZ2, and the seventh p channel FET 1317, denoted by TPZ1, for SZ, as well as the third p channel FET 1307, denoted by TPY2, and the second p channel FET 1306, denoted by TPY1 for SY, are activated.

Thus, the two different threshold voltage configurations

(P21-1) Vth(PZ2)<Vth(PY2); Vth(PZ1)<Vth(PY1), and

(P21-0) Vth(PZ2)>Vth(PY2); Vth(PZ1)>Vth(PY1)

correspond to the two different values X11=0 and X11=1 for the fourth forbidden transition:

(T, S)=(1, 1)→(0, 1)=>(Z, Y)=(1, 1)→(X11, not(X11)).

Since all four relevant pull-up and pull-down paths differ from each other, and can therefore be chosen independently from each other, the four MH secrets, i.e. the values X00, X01, X10 and X11, may also be chosen independently. Thus, for the MH based on self-dual ND2-NR2 gates of FIG. 13, 2⁴=16 different MH incarnations may be realised, i.e. 16 different MH incarnations featuring the same physical layout (i.e. being indistiguishable in terms of their physical design), but exhibiting different electronical behaviour due to their different CMOS threshold voltage configurations. Moreover, the independency of X00, X01, X10 and X11 corresponds to a path-dependeny of the Boolean Secrets, i.e. each secret (X00, X01, X10 and X11) does not only depend on the input control signal state but also on the way this state has been arrived at.

The above illustrates the benefit of the concept of SDBF based MH, compared with MH cells such as the one shown in FIG. 3. Namely, the circuit 300 is a MH cell with two control inputs featuring NI=4 different incarnations and NT=16 MOS FETs, i.e. a MH Efficiency (MHE) of MHE=NI/NT=4/16=0.25.

The corresponding SDBF based MH cell of FIG. 13 also features two control inputs and exhibits NI=16 different incarnations and NT=24 FETs, i.e. a MH Efficiency (MHE) of MHE=NI/NT=16/24=0.667.

That is, for the case of MH circuitry with two control inputs SDBF based MH cell yields an MHE improvement factor of 2.67.

Magic Hoods over self-dual Boolean Functions may be deployed to efficiently generate secret bit strings. For instance, table 1 shows, for the Magic Hood based on self-dual ND2-NR2 gates of FIG. 13, the sequence of its outputs (Z, Y) responding to some of 4!=24 different possible control input sequences.

TABLE 1 cycle (T, S) (Z, Y) (T, S) (Z, Y) . . . (T, S) (Z, Y) 0 (0, 0) (0, 0) (0, 0) (0, 0) . . . (1, 1) (0, 0) 1 (0, 1) (X00, (1, 0) (X01, . . . (1, 0) (X10, not(X00)) not(X01)) not(X10)) 2 (0, 0) (0, 0) (0, 0) (0, 0) . . . (0, 0) (0, 0) 3 (1, 0) (X01, (0, 1) (X00, . . . (0, 1) X00, not(X01)) not(X00)) not(X00)) 4 (1, 1) (1, 1) (1, 1) (1, 1) . . . (1, 1) (1, 1) 5 (1, 0) (X10, (0, 1) (X11, . . . (0, 1) (X11, not(X10)) not(X11)) not(X11)) 6 (1, 1) (1, 1) (1, 1) (1, 1) . . . (0, 0) (1, 1) 7 (0, 1) (X11, (1, 0) (X10, . . . (1, 0) (X01, not(X11)) not(X10)) not(X01))

In this way a relatively small number of Magic Hood cells can be used to generate a large number of secrete bit strings.

Moreover, a SDBF based Magic Hood cell realizes a “covert causality”, i.e., from the state of its outputs (Z, Y) being in one of their “secret” states (X_(ij), NOT(X_(ij))), it is not possible to infer its inputs (T, S).

To further demonstrate the benefit of SDBF based Magic Hood cells, another, slightly more complex example, namely a MH cell featuring multiple feedback paths based on self-dual NAND3-NOR3 (ND3-NR3) gates is described in the following with reference to FIGS. 14 and 15.

FIG. 14 shows a self-dual NAND3-NOR3 gate U_(ND3-NR3) 1400.

The gate 1400 includes a first p channel FET 1401 whose source is connected to the high supply potential and whose gate is supplied with an input signal A, a second p channel FET 1402 whose source is connected to the high supply potential and whose gate is supplied with an input signal B and a third p channel FET 1403 whose source is connected to the high supply potential and whose gate is supplied with an input signal C. The drains of the p channel FETs 1401, 1402, 1403 are connected to the source of a fourth p channel FET 1404 whose gate is supplied with an input signal T and whose drain is connected to an output node 1408 outputting an output signal Z.

The gate 1400 further includes a fifth p channel FET 1405 whose source is connected to the high supply potential, whose gate is supplied with the input signal A and whose drain is conneced to the source of a sixth p channel FET 1406 whose gate is supplied with the input signal B and whose drain is connected to the source of a seventh p channel FET 1407 whose gate is supplied with the input signal B and whose drain is connected to the output node 1408.

Further, the gate 1400 includes a first n channel FET 1409 whose source is connected to the low supply potential and whose gate is supplied with the input signal A, a second n channel FET 1410 whose source is connected to the low supply potential and whose gate is supplied with the input signal B and a third n channel FET 1411 whose source is connected to the low supply potential and whose gate is supplied with the input signal C. The drains of the n channel FETs 1409, 1410, 1411 are connected to the source of a fourth n channel FET 1412 whose gate is supplied with the input signal T and whose drain is connected to the output node 1408.

The gate 1400 further includes a fifth n channel FET 1413 whose source is connected to the low supply potential, whose gate is supplied with the input signal A and whose drain is connected to the source of a sixth n channel FET 1414 whose gate is supplied with the input signal C and whose drain is connected to the source of a seventh n channel FET 1415 whose gate is supplied with the input signal B and whose drain is connected to the output node 1408.

Depending on T, the gate 1400 acts as NAND or NOR gate:

T=0=>U_(ND3-NR3)(T; A, B, C)=NAND3(A, B, C), and

T=1=>U_(ND3-NR3)(T; A, B, C)=NOR3(A, B, C).

FIG. 15 shows a circuit 1500 implementing a Magic Hood cell based on unified NAND3-NOR3 gates featuring multiple feedback paths.

The circuit 1500 includes a first NAND3-NOR3 gate 1501, a second NAND3-NOR3 gate 1502 and a third NAND3-NOR3 gate 1503 as described with reference to FIG. 14.

The output of the first NAND3-NOR3 gate 1501 is denoted by SZ and is inverted by a first inverter 1504 to generate and output signal Z. It is further supplied as input signal A to the second NAND3-NOR3 gate 1502 and as input signal B to the third NAND3-NOR3 gate 1503.

The output of the second NAND3-NOR3 gate 1502 is denoted by SY and is inverted by a second inverter 1505 to generate and output signal Y. It is further supplied as input signal B to the first NAND3-NOR3 gate 1501 and as input signal A to the third NAND3-NOR3 gate 1503.

The output of the third NAND3-NOR3 gate 1503 is denoted by SW and is inverted by a third inverter 1506 to generate and output signal W. It is further supplied as input signal B to the second NAND3-NOR3 gate 1502 and as input signal A to the first NAND3-NOR3 gate 1501.

An input signal S is supplied as input signal C to the NAND3-NOR3 gates 1501, 1502, 1503. Further, the NAND3-NOR3 gates 1501, 1502, 1503 receive an input signal T.

Depending on the control inputs T and S there are the two precharge states

(T, S)=(0, 0)=>(Z, Y, W)=(0, 0, 0) and

(T, S)=(1, 1)=>(Z, Y, W)=(1, 1, 1)

of the three outputs Z, Y and W.

For (T, S)=(0, 1) there are three stable states of the outputs:

(T, S)=(0, 1)=>either

(Z, Y, W)=(1, 0, 0), or

(Z, Y, W)=(0, 1, 0), or

(Z, Y, W)=(0, 0, 1).

For (T, S)=(1, 0) there are the additional three stable states of the outputs:

(T, S)=(1, 0)=>either

(Z, Y, W)=(0, 1, 1), or

(Z, Y, W)=(1, 0, 1), or

(Z, Y, W)=(1, 1, 0).

All six different stable output states can be arrived at from one of the two precharge states:

For the transition (T, S)=(0, 0)→(0, 1) by activating simultaneously all the U_(ND3-NR3) gates' pull-down paths on the right hand side of the gate 1400 (i.e. the serial connection of the three n channel transistors 1413, 1414, 1415);

For the transition (T, S)=(0, 0)→(1, 0) by activating simultaneously all the U_(ND3-NR3) gates' pull-down paths on the left hand side of the gate 1400 (i.e. the serial connection of the fourth n channel FET 1412 and the parallel connection of the three n channel FETs transistors 1409, 1410, 1411);

For the transition (T, S)=(1, 1)→(1, 0) by activating simultaneously all the U_(ND3-NR3) gates' pull-up paths on the right hand side of the gate 1400 (i.e. the serial connection of the three p channel FETs 1405, 1406, 1407);

For the transition (T, S)=(1, 1)→(0, 1) by activating simultaneously all the U_(ND3-NR3) gates' pull-up paths on the left hand side of the gate 1400 (i.e. the serial connection of the fourth p channel FET transistor 1404 and the parallel connection of the three p channel FETs 1401, 1402, 1403);

Thus, by suitably and independently choosing the Vth configurations for all the pairwise different and above indicated pull-up and pull-down paths, 3⁴=81 different incarnations of the U_(ND3-NR3) based MH circuit 1500 can be realised, all of them with identical physical design, but pairwise differing from each other in their forbidden transition behaviour.

This again shows the (exponentially increasing) benefit of the concept of SDBF based MH cells, compared with (not SDBF based) MH cells such as the circuit 1200: The circuit 1500 features two control inputs, and exhibits NI=81 different incarnations and NT=3*16=48 FETs, i.e. a MH Efficiency (MHE) of MHE=NI/NT=81/48=27/16=1.69.

In contrast with that, the circuit 1200 has two control inputs and features NI=9 different incarnations and NT=3*10=30 FETs, i.e. a MH Efficiency (MHE) of MHE=NI/NT=9/30=0.3.

That is, for the case of MH circuitry with two control inputs and three outputs (and feedback paths) the circuit 1500 yields an MHE improvement factor of 5.63.

FIG. 16 shows another example for a gate 1600 representing a self-dual Boolean Function.

The gate 1600 includes a first p channel FET 1601 whose source is connected to the high supply potential, whose gate is supplied with an input signal A and whose drain is connected to the source of a second p channel FET 1602 whose gate is supplied with an input signal B. The gate 1600 further includes a third p channel FET 1603 whose source is connected to the high supply potential and whose gate is supplied with an input signal C.

The drains of the second p channel FET 1602 and the third p channel FET 1603 are connected to the source of a fourth p channel FET 1604 whose gate is supplied with an input signal T and whose drain is connected to an output node 1608 outputting an output signal Z.

The gate 1600 further includes a fifth p channel FET 1605 whose source is connected to the high supply potential and whose gate is supplied with the input signal A and a sixth p channel FET 1606 whose source is connected to the high supply potential and whose gate is supplied with the input signal B. The drains of the fifth p channel FET 1605 and the sixth p channel FET 1606 are connected to the source of a seventh p channel FET 1607 whose gate is supplied with the input signal C and whose drain is connected to the output node 1608.

The gate 1600 further includes a first n channel FET 1609 whose source is connected to the low supply potential, whose gate is supplied with the input signal A and whose drain is connected to the source of a second n channel FET 1610 whose gate is supplied with the input signal B. The gate 1600 further includes a third n channel FET 1611 whose source is connected to the low supply potential and whose gate is supplied with the input signal C

The drains of the second n channel FET 1610 and the third n channel FET 1611 are connected to the source of a fourth n channel FET 1612 whose gate is supplied with the input signal T and whose drain is connected to the output node 1608.

The gate 1600 further includes a fifth n channel FET 1613 whose source is connected to the low supply potential and whose gate is supplied with the input signal A and a sixth n channel FET 1614 whose source is connected to the low supply potential and whose gate is supplied with the input signal B. The drains of the fifth n channel FET 1613 and the sixth n channel FET 1614 are connected to the source of a seventh n channel FET 1615 whose gate is supplied with the input signal C and whose drain is connected to the output node 1608.

The gate 1600 is a U_(OND-ANR) gate unifying the OR-NAND and the AND-NOR function:

T=0=>U_(OND-ANR) (T; A, B, C)=NAND(C, OR(A, B)), and

T=1=>U_(OND-ANR) (T; A, B, C)=NOR(C, AND(A, B)),

i.e. a gate representing both the OR-NAND and the AND-NOR function, depending on the transformation parameter T.

The U_(OND-ANR) gate may be employed in much the same way as above described for Magic Hood circuitry featuring three control inputs.

While specific aspects have been described, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the aspects of this disclosure as defined by the appended claims. The scope is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced. 

What is claimed is:
 1. A method for manufacturing a digital circuit comprising: forming a plurality of field effect transistor pairs; forming one or more pairs of competing paths such that, for each field effect transistor pair, the two field effect transistors are in different competing paths of a pair of competing paths; forming a first sub-circuit of the digital circuit implementing a first Boolean function and a second sub-circuit of the digital circuit implementing a second Boolean function wherein, for each pair of competing paths, one competing path is in the first sub-circuit and one competing path is in the second sub-circuit; connecting the field effect transistors of the field effect transistor pairs such that in response to a first transition from a first state of two nodes of the digital circuit and in response to a second transition from a second state of the nodes of the digital circuit the nodes each have an undefined logic state when, for each field effect transistor pair, the threshold voltages of the field effect transistors of the field effect transistor pair are equal; and setting the threshold voltages of the field effect transistors of the field effect transistor pairs such that the nodes each have a predetermined defined logic state in response to the first transition and in response to the second transition.
 2. The method of claim 1, comprising forming outputs for signals representing the logic states of the nodes.
 3. The method according to claim 2, comprising forming a further circuit component and a connection for supplying the signal to the further circuit component.
 4. The method according to claim 3, wherein the further circuit component is a logic gate.
 5. The method according to claim 3, wherein the further circuit component is a flip-flop.
 6. The method according to claim 1, wherein, for each field effect transistor pair, the two field effect transistors of the field effect transistor pair are both n channel field effect transistors or the two field effect transistors of the field effect transistor pair are both p channel field effect transistors.
 7. The method according to claim 1, wherein the field effect transistors of the field effect transistor pairs are MOSFETs.
 8. The method according to claim 1, comprising connecting the one or more pairs of competing paths such that the logic states of the nodes depend on the result of the competition between the competing paths of the one or more pairs of competing paths.
 9. The method of claim 1, comprising connecting the one or more pairs of competing paths and the nodes such that for each pair of competing paths, the competing paths are connected to different ones of the two nodes and the electrical state of the node connected to one of the competing paths is fed back to the other of the competing paths to hinder it in a competition of the competing paths.
 10. The method of claim 1, comprising connecting an output of the first sub-circuit with an input of the second sub-circuit and an output of the second sub-circuit with an input of the first sub-circuit.
 11. The method of claim 1, wherein the first Boolean function and the second Boolean function are self-dual Boolean functions.
 12. The method of claim 1, wherein the first Boolean function and the second Boolean function are the same Boolean function.
 13. The method of claim 1, wherein the plurality of field effect transistor pairs comprises one or more pull-up field effect transistor pairs each having a field effect transistor in a first pull-up path and a field effect transistor in a second pull-up path and comprising connecting the first pull-up path to one of the two nodes and the second pull-up path to the other of the two nodes.
 14. The method of claim 13, comprising setting, for each pull-up field effect transistor pair, the threshold voltage of the field effect transistor in the first pull-up path to be lower than the threshold voltage of the field effect transistor in the second pull-up path.
 15. The method of claim 1, wherein the plurality of field effect transistor pairs comprises one or more pull-down field effect transistor pairs each having a field effect transistor in a first pull-down path and a field effect transistor in a second pull-down path and comprising connecting the first pull-down path to one of the two nodes and the second pull-down path to the other of the two nodes.
 16. The method of claim 15, comprising setting, for each pull-down field effect transistor pair, the threshold voltage of the field effect transistor in the first pull-down path to be lower than the threshold voltage of the field effect transistor in the second pull-down path.
 17. The method of claim 1, comprising connecting the field effect transistors of the field effect transistor pairs to pull-up paths and pull-down paths connected to the two nodes and setting the threshold voltages of the field effect transistors of the pull-up paths independently from the threshold voltages of the field effect transistors of the pull-down paths.
 18. The method according to claim 1, comprising forming the plurality of field effect transistors in CMOS technology.
 19. The method according to claim 1, wherein, for each of the nodes, the predetermined defined logic state is a logic 0 or a logic
 1. 20. The method according to claim 1, wherein, for each field effect transistor pair, the field effect transistors of the field effect transistor pair are formed to substantially have the same dimensions.
 21. The method according to claim 1, comprising forming the digital circuit such that the first transition and the second transition occur in response to a predetermined input, comprising one or more input signals supplied to field effect transistors of the field effect transistor pairs.
 22. The method of claim 1, wherein the first transition is a pulling up of the nodes and the method comprises connecting the nodes such that, when one of the nodes has been pulled up, it prevents the other node from being pulled up.
 23. The method of claim 1, wherein the second transition is a pulling down of the nodes and the method comprises connecting the nodes such that, when one of the nodes has been pulled down, it prevents the other node from being pulled down.
 24. A digital circuit comprising: a plurality of field effect transistor pairs; one or more pairs of competing paths such that, for each field effect transistor pair of the plurality of field effect transistor pairs, the two field effect transistors are in different competing paths of a pair of competing paths; a first sub-circuit implementing a first Boolean function and a second sub-circuit implementing a second Boolean function wherein, for each pair of competing paths, one competing path is in the first sub-circuit and one competing path is in the second sub-circuit; wherein the field effect transistor pairs comprise field effect transistors connected such that in response to a first transition from a first state of two nodes of the digital circuit and in response to a second transition from a second state of the nodes of the digital circuit the nodes each have an undefined logic state when, for each field effect transistor pair, the threshold voltages of the field effect transistors of the field effect transistor pair are equal; wherein, for each field effect transistor pair, the threshold voltages of the field effect transistors of the field effect transistor pair differ by at least 10 mV such that the nodes each have a predetermined defined logic state in response to the first transition and in response to the second transition.
 25. The digital circuit of claim 24, wherein, for each field effect transistor pair, the threshold voltages of the field effect transistors of the field effect transistor pair differ by at least 20 mV, differ by at least 30 mV or differ by at least 50 mV. 